Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributor'Process' way of work
Hi, I'm having a problem concerning VHDL understanding of the 'Process' way of work. Inside the Process, I assigned "idan_input" into "idan_input_buff" (after the "elsif clk'event and clk='1' th...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- because you have assigned Idan_Input using time, rather than making it relative to the clock, what josb said happens - clock and the input rise at the same time, so the process things that Idan_Input has risen before the clock. --- Quote End --- It is not the 'process' that thinks that the input is one at the time of rising clock but the 'simulator'.
