Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

'Process' way of work

Hi, I'm having a problem concerning VHDL understanding of the 'Process' way of work. Inside the Process, I assigned "idan_input" into "idan_input_buff" (after the "elsif clk'event and clk='1' th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Both your clock input and signal input rise at the same moment. The RTL simulation sees the clock rising and then checks in zero-delay the state of the signal but this has risen at the same time as the clock and the simulator sees a '1' ...