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Altera_Forum
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13 years ago

'Process' way of work

Hi, I'm having a problem concerning VHDL understanding of the 'Process' way of work. Inside the Process, I assigned "idan_input" into "idan_input_buff" (after the "elsif clk'event and clk='1' th...
Altera_Forum's avatar
Altera_Forum
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13 years ago

because you have assigned Idan_Input using time, rather than making it relative to the clock, what josb said happens - clock and the input rise at the same time, so the process things that Idan_Input has risen before the clock.