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Altera_Forum
Honored Contributor
14 years ago'Process' way of work
Hi, I'm having a problem concerning VHDL understanding of the 'Process' way of work. Inside the Process, I assigned "idan_input" into "idan_input_buff" (after the "elsif clk'event and clk='1' th...
Altera_Forum
Honored Contributor
14 years agoyou would not burn the testbench to the target. and it should work as you expect