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Altera_Forum
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14 years ago

'Process' way of work

Hi, I'm having a problem concerning VHDL understanding of the 'Process' way of work. Inside the Process, I assigned "idan_input" into "idan_input_buff" (after the "elsif clk'event and clk='1' th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

a QaD fix is to slightly offset the timing of the input signal by adding e.g. 25 nsec to the times specified. 

Idan_Input <='0', '1' after 1000.025 us,  --(1/700Hz=1428usec,1428usec/2= 714usec, 714usec+1000us=1714usec) 
					   '0' after 1714.025 us, 
					   '1' after 10100.025 us, --(100000*0.1usec=10000mac counter)
					   '0' after 10814.025 us,
					   '1' after 11528.025 us,
					   '0' after 12242.025 us,
					   '1' after 12956.025 us;	--at lest 14000000 nsec simulation runinig time