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Altera_Forum
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14 years ago

problems: object "std_logic" is not declared

Hi;

I try write a code for convert integer to ufixed:

package my_data_types is

type vector is array (natural range <>) of integer;

type ufixed is array (natural range <>) of std_logic;

end my_data_types;

library ieee;

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

use work.my_data_types.all;

entity fix is

port (clk: in bit;

nprev: in vector (0 to 7);

ip1: out ufixed (3 downto -4));

end fix;

architecture fix of fix is

signal n1: ufixed (3 downto -4);

begin

process(clk)

begin

if (clk'event and clk='1') then

for i in 0 to 7 loop

ip1(i) <= to_ufixed (nprev(i),n1);

end loop;

end if;

end process;

end fix;

I get this error:

Error (10482): VHDL error at fix.vhd(3): object "std_logic" is used but not declared.

How to declare the "std_logic" in package?..

16 Replies

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    you clearly didnt for the package. you have to have separate library imports for each package and entity

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    What do you mean by "separate library imports for each package and entity"?

    Thanks for reply
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    in your code, you have the package above the library includes.

    you need to do this: 

    
--libraries for the package
library ieee;
use ieee.std_logic_1164.all;
library IEEE_Porposed;
use IEEE_Proposed.fixed_pkg.all;
package my_package is
....
end package;
--Now the libraries for the entity
library ieee;
use ieee.std_logic_1164.all;
library IEEE_Porposed;
use IEEE_Proposed.fixed_pkg.all;
use work.my_package.all;

    Usually, you would put the package and entity in a separate file.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    May I suggest you read a VHDL tutorial - a lot of the questions you are asking are very very basic.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Yes, I will. Since now, I still learn form vhdl tutorial and other materials for my better understand.Thanks for the advise =)