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Altera_Forum
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14 years ago

problems: object "std_logic" is not declared

Hi; I try write a code for convert integer to ufixed: package my_data_types is type vector is array (natural range <>) of integer; type ufixed is array (natural range <>) of std_logic; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Yes, I will. Since now, I still learn form vhdl tutorial and other materials for my better understand.Thanks for the advise =)