Altera_ForumHonored Contributor14 years agoproblems: object "std_logic" is not declared Hi; I try write a code for convert integer to ufixed: package my_data_types is type vector is array (natural range <>) of integer; type ufixed is array (natural range <>) of std_logic; ...Show More
Recent DiscussionsSDRAM ( Single Data Rate ) refresh verilogadding signal to debug/signaltapSDM & Configuration InterfaceNeed Part EOL status(Active/Obsolete/Discontinued/NRND)Agilex 7 JTAG Config Fails at 1% on Board #2 (Error 18950 / CONF_DONE Low) - But Board #1 Works