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Altera_Forum
Honored Contributor
Honored Contributorproblems: object "std_logic" is not declared
Hi; I try write a code for convert integer to ufixed: package my_data_types is type vector is array (natural range <>) of integer; type ufixed is array (natural range <>) of std_logic; ...
Altera_ForumHonored Contributor
Honored Contributoryou clearly didnt for the package. you have to have separate library imports for each package and entity
