Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

problems: object "std_logic" is not declared

Hi; I try write a code for convert integer to ufixed: package my_data_types is type vector is array (natural range <>) of integer; type ufixed is array (natural range <>) of std_logic; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

May I suggest you read a VHDL tutorial - a lot of the questions you are asking are very very basic.