problems: object "std_logic" is not declared

Hi;

I try write a code for convert integer to ufixed:

package my_data_types is

type vector is array (natural range <>) of integer;

type ufixed is array (natural range <>) of std_logic;

end my_data_types;

library ieee;

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

use work.my_data_types.all;

entity fix is

port (clk: in bit;

nprev: in vector (0 to 7);

ip1: out ufixed (3 downto -4));

end fix;

architecture fix of fix is

signal n1: ufixed (3 downto -4);

begin

process(clk)

begin

if (clk'event and clk='1') then

for i in 0 to 7 loop

ip1(i) <= to_ufixed (nprev(i),n1);

end loop;

end if;

end process;

end fix;

I get this error:

Error (10482): VHDL error at fix.vhd(3): object "std_logic" is used but not declared.

How to declare the "std_logic" in package?..