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Altera_Forum
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14 years ago

problems: object "std_logic" is not declared

Hi; I try write a code for convert integer to ufixed: package my_data_types is type vector is array (natural range <>) of integer; type ufixed is array (natural range <>) of std_logic; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

This is my package code:

package my_data_types is

type vector is array (natural range <>) of integer;

type ufixed_array_t is array (natural range <>) of ufixed (3 downto -4);

end my_data_types;

But then, error said:

Error (10482): VHDL error at fix.vhd(3): object "ufixed" is used but not declared

How to avoid this error?..Thanks for reply