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Altera_Forum
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14 years ago

problems: object "std_logic" is not declared

Hi; I try write a code for convert integer to ufixed: package my_data_types is type vector is array (natural range <>) of integer; type ufixed is array (natural range <>) of std_logic; ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Now I get this error:

Error (10511): VHDL Qualified Expression error at fix.vhd(23): to_ufixed type specified in Qualified Expression must match std_ulogic type that is implied for expression by context.

At this line: ip1(i) <= to_ufixed (nprev(i),n1);

Why?..thanks for reply