please explain use of set_output_delay

Brad,

No, I don't think so. I'm sure you know but Tco is clock to output delay. So, maximum Tco is simply the worst case clock to output delay for the sending end. i.e. from clock transition to data transition.

I think the slowest and fastest regions are simply the data valid regions for the extremes of Tco.

Regards,

D

In gee's attachment, the Min_Tco arrow goes to the left side of the "Fastest" transition region, which is correct. (Min_Tco is how long old data remains valid before the pin starts changing for new data.)

The Max_Tco arrow goes to the left side of the "Slowest" transition region. Shouldn't it go to the right side?

Thanks gee,

yes this helps from the set_output_delay point of view.

Many thanks,

D.

Hi,

Does the explanation attached make sense for you? The input delay is different and adds to arrival time while the output delay subtracts from required time.

Thanks Brad, but having thought about it I think my question boils down to this simple one and I know I won't be happy unless I understand the answer:

for set_output_delay:

does -max specify the most positive/least negative i.e. earliest time at which data can arrive wrt the clock ?

does -min specify the least positive/most negative i.e. latest time at which data can arrive wrt the clock ?

AND, does this convention also apply in exactly the same way to set_input_delay?

Regards,

D.

--- Quote Start ---

output delay max = board delay (max) - board clock skew (min) + tsu (external device)

...

tCO Requirement set_output_delay -max <latch &#8722; launch &#8722; tCO requirement>

why does <latch - launch> come in to it? Isn't "set_output_delay - max" equivalent to defining the tcomax?

--- Quote End ---

For a common simple case, the source register driving out from the FPGA and the destination register receiving in the external device are using the same clock, and a single clock period is allowed (no multicycle). For that case, "latch - launch" is one clock period. set_output_delay -max is one clock period minus the FPGA's tco. If the board delays are ignored, then set_output_delay -max is also the same as the tsu of the external device--FPGA tco plus external device tsu equals one clock period.

For set_output_delay -min in this simple case, "latch - launch" is zero.

Table 7-4 in the Quartus handbook gives you the conversion between set_output_delay and tco/min tco in terms of latch and launch to cover more cases like where a PLL in the FPGA makes "latch - launch" be something different from a simple single clock period for max or zero for min.

Hang on, I think I may be getting it. Is this correct?

set_output_delay specifies the minimum and maximum data arrival times wrt the clock.

so a maximum value is the value most ahead of the clock. +ve values before the clock and -ve values after the clock. This would explain my misunderstanding I think.

I'd be grateful if someone could confirm this or put me right...