Honored ContributorI have a Cyclone III FPGA. I want to output a clock, lets say a SCLK for SPI communication, from the FPGA to another device. Should I use a PLL output pin or can I just use a normal IO? The clock signal is single ended (not differential) and will be a maximum of 60 MHz. Thank you
Honored ContributorYou can drive a clock out via any IO pin, but Altera recommends to do it with ddr_out block to get an optimal result (without warnings about jitter etc.).
Honored ContributorThe use of DDR to clock out is justified for very high speed.
SPI clocks are normally very slow and so any io will doHonored ContributorRight, wanted to say that too. DDR in fact is only a must, when putting out the clock frequency itself. Everything lower, which is a 100% divider of the master clock is best realized with a counter and a simple IO-REG (FF).
Another case may be a clock of e.g. 66% of the system clock. A DDR and another PLL will be required.Honored ContributorWhat's the flak for?
Danieldt said he wants to output a 60 MHz clock to drive an SPI device (e.g. a Serial Data Flash) and I assumed this clock is probably generated by a PLL. If you output the clock directly to an IO pin the fitter will issue a warning that the that output signal has increased jitter. If you subsequently use a ddr-Out bock to drive that clock out, the warning will disappear. I don't like warnings to appear from code I write, so I put in the ddr-out block. It is not because Altera's IP (and others too, I know) spits out zillions of cryptic warnings that we should allow our work to do the same.
