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Altera_Forum
Honored Contributor
Honored ContributorOutputting a clock
I have a Cyclone III FPGA. I want to output a clock, lets say a SCLK for SPI communication, from the FPGA to another device. Should I use a PLL output pin or can I just use a normal IO? The clock sig...
Altera_ForumHonored Contributor
Honored ContributorWhat's the flak for?
Danieldt said he wants to output a 60 MHz clock to drive an SPI device (e.g. a Serial Data Flash) and I assumed this clock is probably generated by a PLL. If you output the clock directly to an IO pin the fitter will issue a warning that the that output signal has increased jitter. If you subsequently use a ddr-Out bock to drive that clock out, the warning will disappear. I don't like warnings to appear from code I write, so I put in the ddr-out block. It is not because Altera's IP (and others too, I know) spits out zillions of cryptic warnings that we should allow our work to do the same.
