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Altera_Forum
Honored Contributor
Honored ContributorOutputting a clock
I have a Cyclone III FPGA. I want to output a clock, lets say a SCLK for SPI communication, from the FPGA to another device. Should I use a PLL output pin or can I just use a normal IO? The clock sig...
Altera_ForumHonored Contributor
Honored ContributorYou can drive a clock out via any IO pin, but Altera recommends to do it with ddr_out block to get an optimal result (without warnings about jitter etc.).
