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Altera_Forum
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16 years ago

Outputting a clock

I have a Cyclone III FPGA. I want to output a clock, lets say a SCLK for SPI communication, from the FPGA to another device. Should I use a PLL output pin or can I just use a normal IO? The clock sig...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Right, wanted to say that too. DDR in fact is only a must, when putting out the clock frequency itself. Everything lower, which is a 100% divider of the master clock is best realized with a counter and a simple IO-REG (FF).

Another case may be a clock of e.g. 66% of the system clock. A DDR and another PLL will be required.