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Honored ContributorMy Clock Divider with enable doesn't work
Dear all, I tried to do clock divider with enable, as suggested by many previous posts, but still doesn't work , still has the same warning, anybody can help me? Thank you very much!
process(CLK,System_enable) begin if System_enable='0' then CLKDiv<= "00000000000000"; elsif(rising_edge(CLK)) then if CLKDiv="0000000000011"then CLKDiv<="00000000000000"; CLKenable <= '1'; else CLKDiv<=CLKDiv + 1; Clkenable <= '0'; end if; end if; end process; process (CLK, Clkenable,System_enable) begin if (System_enable = '0') then CLK4T <= '0'; elsif (rising_edge(CLK)) then if (Clkenable = '1') then CLK4T <= not CLK4T; end if; end if; end process; Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock "CLK4T" as buffer7 Replies
Altera_ForumTry this version: I didn't test it but it gives the idea
process(CLK,System_enable) begin if System_enable = '0' then CLKDiv <= "0000000000"; -- 10 bit counter CLKDiv_d <= "0000000000"; elsif(rising_edge(CLK)) then CLKDiv <= CLKDiv + 1; CLKDiv_d <= CLKDiv; end if; end process; process (CLK) begin if (rising_edge(CLK)) then if ( CLKDiv(0) = '1') then -- 1/2 clk ...... ...... end if; if ( CLKDiv(1) = '1' and CLKDiv_d(1) = '0') then -- 1/4 clk ...... ...... end if; if ( CLKDiv(2) = '1' and CLKDiv_d(2) = '0') then -- 1/8 clk ...... ...... end if; ...... end if; end process;- Altera_Forum
Thanks, so it is not possible? Do you know how to use the in-chip clock divider in Max II
It has "- four global clock
- Clock divider (÷ 2,4,6,8,10,12,14,16)"
- Altera_Forum
Your original code was creating lower speed clocks. That's perfectly do-able. But now you have multiple clock domains all taking different paths through general purpose logic. This creates significant clock skew between each domain. This causes positive hold requirements, can cut into setup requirements, etc. Basically it can cause timing nightmares. Now, the tools have gotten much better at analyzing and correcting these issues, but it's a potentially large burden on the tools, and it often requires a better understanding of these issues by the designer. If everything is on a single global clock, then the skew is so small there are no hold violations and everything just works out.
- Altera_Forum
Thanks, if there anyway which I can use a signal just as a clock input to drive process while it is 1/4, 1/8 ... of Oscillator frequency? if no PLL?
--- Quote Start --- I still don't get why CLKDiv is so large, since it will reset after reaching 4, i.e. it will never reach 8, 16, etc. Anyway, if you want all of these off of one divider, then just have ClkDiv count, and don't put the enable in that clocked process. And if the max divide is 512, then have it count to 511 and then reset. Outside of the process have: Enable4T <= '1' when (CLKDiv(1 downto 0) = "11") else '0'; Enable8T <= '1' when (ClkDiv(2 downto 0) = "111") else '0'; etc. This will create a pulse everytime those conditions are met. Then for logic that needs to run at the 1/4th rate, have: elsif (rising_edge(CLK)) then if (Enable4T = '1') then (insert slower logic here) I would have a separte process for each enable. (You can probably combine them, just advise against for clarity) --- Quote End --- - Altera_Forum
I still don't get why CLKDiv is so large, since it will reset after reaching 4, i.e. it will never reach 8, 16, etc. Anyway, if you want all of these off of one divider, then just have ClkDiv count, and don't put the enable in that clocked process. And if the max divide is 512, then have it count to 511 and then reset.
Outside of the process have: Enable4T <= '1' when (CLKDiv(1 downto 0) = "11") else '0'; Enable8T <= '1' when (ClkDiv(2 downto 0) = "111") else '0'; etc. This will create a pulse everytime those conditions are met. Then for logic that needs to run at the 1/4th rate, have: elsif (rising_edge(CLK)) then if (Enable4T = '1') then (insert slower logic here) I would have a separte process for each enable. (You can probably combine them, just advise against for clarity) - Altera_Forum
Yes, I am using 1/4 of Oscillator frequency to drive another process. I saw a lot of people use clock divider with enable, how they do that?
The reason for CLKDiv so large is because we still want 1/4, 1/8, 1/16, 1/32, .... 1/256, 1/512... clock divider to drive another process. It is a Max II. Maybe don't have PLL. --- Quote Start --- Are you using CLK4T as the clock in another process? If so, that's what the warning is about. If CLK is the only clock in the design, it should be the only one thing used in a (rising_edge) statement. It might be best to think of it like a schematic, where you've created CLK4T. When that is used in other logic, it will not feed the clock port(i.e. rising_edge), but will be a conditional right after the rising_edge statement. Out of curiosity, why is CLKDiv so large when it seems to count to 11 and then reset to 0? I imagine the rest of it will get synthesized out, but seems strange. --- Quote End --- - Altera_Forum
Are you using CLK4T as the clock in another process? If so, that's what the warning is about. If CLK is the only clock in the design, it should be the only one thing used in a (rising_edge) statement. It might be best to think of it like a schematic, where you've created CLK4T. When that is used in other logic, it will not feed the clock port(i.e. rising_edge), but will be a conditional right after the rising_edge statement.
Out of curiosity, why is CLKDiv so large when it seems to count to 11 and then reset to 0? I imagine the rest of it will get synthesized out, but seems strange.
