My Clock Divider with enable doesn't work

Thanks, if there anyway which I can use a signal just as a clock input to drive process while it is 1/4, 1/8 ... of Oscillator frequency? if no PLL?

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I still don't get why CLKDiv is so large, since it will reset after reaching 4, i.e. it will never reach 8, 16, etc. Anyway, if you want all of these off of one divider, then just have ClkDiv count, and don't put the enable in that clocked process. And if the max divide is 512, then have it count to 511 and then reset.

Outside of the process have:

Enable4T <= '1' when (CLKDiv(1 downto 0) = "11") else '0';

Enable8T <= '1' when (ClkDiv(2 downto 0) = "111") else '0';

etc.

This will create a pulse everytime those conditions are met.

Then for logic that needs to run at the 1/4th rate, have:

elsif (rising_edge(CLK)) then

if (Enable4T = '1') then

(insert slower logic here)

I would have a separte process for each enable. (You can probably combine them, just advise against for clarity)

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