My Clock Divider with enable doesn't work

Yes, I am using 1/4 of Oscillator frequency to drive another process. I saw a lot of people use clock divider with enable, how they do that?

The reason for CLKDiv so large is because we still want 1/4, 1/8, 1/16, 1/32, .... 1/256, 1/512... clock divider to drive another process.

It is a Max II. Maybe don't have PLL.

--- Quote Start ---

Are you using CLK4T as the clock in another process? If so, that's what the warning is about. If CLK is the only clock in the design, it should be the only one thing used in a (rising_edge) statement. It might be best to think of it like a schematic, where you've created CLK4T. When that is used in other logic, it will not feed the clock port(i.e. rising_edge), but will be a conditional right after the rising_edge statement.

Out of curiosity, why is CLKDiv so large when it seems to count to 11 and then reset to 0? I imagine the rest of it will get synthesized out, but seems strange.

--- Quote End ---