My Clock Divider with enable doesn't work

Thanks, so it is not possible? Do you know how to use the in-chip clock divider in Max II

It has "

• four global clock

• Clock divider (÷ 2,4,6,8,10,12,14,16)"

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Your original code was creating lower speed clocks. That's perfectly do-able. But now you have multiple clock domains all taking different paths through general purpose logic. This creates significant clock skew between each domain. This causes positive hold requirements, can cut into setup requirements, etc. Basically it can cause timing nightmares. Now, the tools have gotten much better at analyzing and correcting these issues, but it's a potentially large burden on the tools, and it often requires a better understanding of these issues by the designer. If everything is on a single global clock, then the skew is so small there are no hold violations and everything just works out.

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