Multiplexer Output Glitching

Avoiding glitches in combinatorial circuits brings you into the field of "Asynchronous Sequential Switching Circuits" and "Asynchronous State Machines". Rewriting the equation will not really help as everything depends on the relative path delays as produced by the fitter and these will vary while compiling the design after each design change/addition.

Yes, that is my thoughts too. In my test bench, only one of my inputs is changing so why the glitch? It is moving from one row in the LUT to another with only one input changing so I would have thought that there shouldn't be a glitch.

Ok, I've been playing some more and have used three 2 to 1 multiplexers to create the 4 to 1 and have used the /* synthesis keep */; trick (thanks FvM) so that the 2 to 1 mux's don't get reduced. This now seems to work as I require i.e. it is glitch free so it solves my problem. However, I still don't understand why my original code glitches. If two inputs changed at once, I could understand the glitch if the output from only one input change was different but this isn't the case.

module multiplexertest (
    input wire a,b,c,d,
    input wire s,t,
    output wire q
);
    wire x,y /* synthesis keep */;
    assign x = (t) ? d : c;
    assign y = (t) ? b : a;
    assign q = (s) ? x : y;
endmodule

From the Quartus Help:

module multiplexertest (
    input wire a,b,c,d,
    input wire s,t,
    output wire q , q2
);
    assign q = (s) ?
                ((t) ? d : c) :
                ((t) ? b : a);
                
    assign q2 =	   !s && !t && a
		|| !s &&  t && b
		||  s && !t && c
		||  s &&  t && d
		;
endmodule

Thanks for having a play josyb, it is appreciated.

`timescale 1 ns /  100 ps
module multiplexertest_TB ();
    reg a,b,c,d;
    reg s,t;
    wire q;
    multiplexertest multiplexertest_inst
    (
        .a(a) ,    // input  a_sig
        .b(b) ,    // input  b_sig
        .c(c) ,    // input  c_sig
        .d(d) ,    // input  d_sig
        .s(s) ,    // input  s_sig
        .t(t) ,    // input  t_sig
        .q(q)     // output  q_sig
    );
    initial begin
        a = 1;
        b = 0;
        c = 0;
        d = 1;
        s = 0;
        t = 0;
    end
    always begin
       # 40 t = !t;
        s = !s;
    end
    
endmodule

I did some variations as well. (Always fun to learn something on a Sunday afternoon! Verilog is still new to me so I used this occasion to study it a tiny bit)) See the attached QAR.

Thanks for that.

That's funny, in my simulation (using Quartus 9.1sp2 internal simulator) it is q4 and q5 that are glitch free even for the simultaneous changing of 's' and 't'.

Interesting. I'm using Quartus 10.0 and Model Sim Altera SE.