Multiplexer Output Glitching

Thanks for having a play josyb, it is appreciated.

I've tried all sorts of arrangements for the 4 to 1 (though not yours...) and all suffer from the same problem as I would guess that they synthesize into the same thing. I now have a solution that appears to work (see above) but I am not sure that it is guaranteed to work as I don't understand the mechanism as to why it is glitching. Putting in delays may well cure it but again I'm not sure it is a robust solution.

If you change the testbench code to the following then I would expect glitching as two inputs are changing at once and it transits through a state with a different output. Interestingly, this produces glitches that are 7ns in size compared to the 1ns glitches I was seeing initially.

`timescale 1 ns /  100 ps
module multiplexertest_TB ();
    reg a,b,c,d;
    reg s,t;
    wire q;
    multiplexertest multiplexertest_inst
    (
        .a(a) ,    // input  a_sig
        .b(b) ,    // input  b_sig
        .c(c) ,    // input  c_sig
        .d(d) ,    // input  d_sig
        .s(s) ,    // input  s_sig
        .t(t) ,    // input  t_sig
        .q(q)     // output  q_sig
    );
    initial begin
        a = 1;
        b = 0;
        c = 0;
        d = 1;
        s = 0;
        t = 0;
    end
    always begin
       # 40 t = !t;
        s = !s;
    end
    
endmodule