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Altera_Forum
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15 years ago

Multiplexer Output Glitching

Hi all, I'm having trouble multiplexing a number of signals without the output glitching. The following 4 to 1 multiplexer with all the inputs connected to 1 shows the issue: module mult...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I did some variations as well. (Always fun to learn something on a Sunday afternoon! Verilog is still new to me so I used this occasion to study it a tiny bit)) See the attached QAR.

If you simulate the design you will see that the 'keep' directive doesn't always work either ...

I notice that on every compile/addition the behavior changes slightly and glitching either disappears or reappears.