Multiplexer Output Glitching

I did some variations as well. (Always fun to learn something on a Sunday afternoon! Verilog is still new to me so I used this occasion to study it a tiny bit)) See the attached QAR.

If you simulate the design you will see that the 'keep' directive doesn't always work either ...

I notice that on every compile/addition the behavior changes slightly and glitching either disappears or reappears.