Multiplexer Output Glitching

From the Quartus Help:

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You can use this synthesis attribute to keep a combinational node so you can observe the node during simulation or with the SignalTap II Logic Analyzer.

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I interpret this that the Fitter/Router will 'keep' said wire/signal but it will not prevent the Fitter/Router from placing it differently on a subsequent compile.

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But at least, when more than one module input signals are changing at the same time, it can't work any more.

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Isn't that the nature of an asynchronous circuit?

To Bat Technologies: You have created a two-step solution which you can assess by viewing your design in the RTL Viewer. Before my first reply I first tried a few things in Quartus myself and rewrote your equation into a single step one. I add the code for your perusal:

module multiplexertest (
    input wire a,b,c,d,
    input wire s,t,
    output wire q , q2
);
    assign q = (s) ?
                ((t) ? d : c) :
                ((t) ? b : a);
                
    assign q2 =	   !s && !t && a
		|| !s &&  t && b
		||  s && !t && c
		||  s &&  t && d
		;
endmodule

At first compile q2 was as glitchy as q. I then added a 5.000 ns tpd (for a CycloneII auto device) and then q2 becomes glitch-free. But I'm not sure whether this will stay this way.