Multiplexer Output Glitching

Ok, I've been playing some more and have used three 2 to 1 multiplexers to create the 4 to 1 and have used the /* synthesis keep */; trick (thanks FvM) so that the 2 to 1 mux's don't get reduced. This now seems to work as I require i.e. it is glitch free so it solves my problem. However, I still don't understand why my original code glitches. If two inputs changed at once, I could understand the glitch if the output from only one input change was different but this isn't the case.

module multiplexertest (
    input wire a,b,c,d,
    input wire s,t,
    output wire q
);
    wire x,y /* synthesis keep */;
    assign x = (t) ? d : c;
    assign y = (t) ? b : a;
    assign q = (s) ? x : y;
endmodule