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Rewriting the equation will not really help as everything depends on the relative path delays as produced by the fitter and these will vary while compiling the design after each design change/addition.
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Depends on.
Glitches can be generally expected, when more than one input of a FPGA LUT are changing simultaneously. This can be avoided at least for the present test case, if you control the logic synthesis by defining nodes with a keep attribute. But at least, when more than one module input signals are changing at the same time, it can't work any more.
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