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Altera_Forum
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15 years ago

Multiplexer Output Glitching

Hi all, I'm having trouble multiplexing a number of signals without the output glitching. The following 4 to 1 multiplexer with all the inputs connected to 1 shows the issue: module mult...
Altera_Forum's avatar
Altera_Forum
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15 years ago

That's funny, in my simulation (using Quartus 9.1sp2 internal simulator) it is q4 and q5 that are glitch free even for the simultaneous changing of 's' and 't'.

If you inspect the Netlist, first RTL and then the Technology map you will find that some of the fitted/routed results aren't that different from the other.

If you look in the tpd report of the timing analyzer you will see that the respective tpd's for 's' and 't' to q4 and q5 are very close together explaining why they seem to be glitchfree, but in real life for some sequence of 's' and 't' changing a glitch will show up.

If you definitely ned absolutely glitchfree outputs you will have to do some reading on asynchronous sequential circuits like I mentioned before. This link (http://web.cecs.pdx.edu/~mperkows/class_573/febr-2007/ieee-asyntutorial.pdf) shows how an asynchronous state machine only differs slightly for a synchronous one idea-wise, but implementation is a different story.