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Altera_Forum
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16 years ago

Multiple LVDS inputs from Multiple sources- without DPA support

Hi

i have a design working with Stratix II FPGA , it uses 44 LVDS inputs using DPA receiver for each ,

(eleven source , different distances, each sending 4 LVDS lines)

now trying to find a solution using arria II GX or Startix IV GX - there are not enough DPA's ( unless going to very very expensive devices)

is there a way to have some sort of clock syncronization in the FPGA Raw LVDS's in these devices ?

what's the usage of all the LVDS inputs in the Raws of the FPGA if it doesn't have a DPA ?

thanks

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    What's the data rate? Are the 11 sources all clocked off the same source clock? If they were completely independent and you absolutely needed DPA, then you would need 11 left/right PLLs, which I don't think any device has. I assume a single PLL/DPA can capture multiple inputs?

    Can your sources send a clock signal, or is it just data with each?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi

    all the LVDS use the same clock frequency,but each four pack travels different distance, even from different boards,

    its about 150-200Mhz DDR (up to 400Mbps).

    (I'm not sending Clock attached to the data , I'm using the DPA to receive all of them)

    even If I will send clock (sending the data at higher freq and using one of the lines as clock) -

    then I will need 11 clock inputs and 11 PLL's..
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Same clock frequency with 0PPM difference(i.e. they all originate from the same clock source) or same frequency, but they'll all vary over time because they come from different clock sources?

    What size device/package are you looking at? Naturally you want to use the True LVDS on the rows, but if there's not enough, you could put some of the interfaces on the columns and use external resistors. For those you won't use DPA and instead would use regular source-synchronous, which I believe you should be able to do at those rates pretty easily. It will require a PLL per/interface for the source synchronous stuff.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    So if I understand correctly, you only needed the DPA but not soft-CDR. In other words, your receive clock is either the same clock or at least locked to the transmit clock. Where is it you are running out of DPA. Each row receiver has its own DPA circuitry. Your only problems would be if you run out of row I/O.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi

    I'm using the same clock for all ( transmitters and receivers)

    currently using stratix II 30 672 pin , now trying to move to stratix IV GX or Arria II Gx, with 700-1100 pins , chip as possible,

    If I'll use the column LVDs then I will need a PLL for each of the sources (4 lines group) ,since each 4 lines are coming from different source ,

    this will consume PLLs, and also doesn't give me any real time phase alignment ..

    to what clock freq can I use the column LVDSs ?

    thanks