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Altera_Forum
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16 years ago

Multiple LVDS inputs from Multiple sources- without DPA support

Hi i have a design working with Stratix II FPGA , it uses 44 LVDS inputs using DPA receiver for each , (eleven source , different distances, each sending 4 LVDS lines) now trying to find a ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

So if I understand correctly, you only needed the DPA but not soft-CDR. In other words, your receive clock is either the same clock or at least locked to the transmit clock. Where is it you are running out of DPA. Each row receiver has its own DPA circuitry. Your only problems would be if you run out of row I/O.

Jake