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Altera_Forum
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16 years ago

Multiple LVDS inputs from Multiple sources- without DPA support

Hi i have a design working with Stratix II FPGA , it uses 44 LVDS inputs using DPA receiver for each , (eleven source , different distances, each sending 4 LVDS lines) now trying to find a ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi

all the LVDS use the same clock frequency,but each four pack travels different distance, even from different boards,

its about 150-200Mhz DDR (up to 400Mbps).

(I'm not sending Clock attached to the data , I'm using the DPA to receive all of them)

even If I will send clock (sending the data at higher freq and using one of the lines as clock) -

then I will need 11 clock inputs and 11 PLL's..