Forum Discussion
Honored Contributormultiple clocks
Hi:
I have two clocks in my design ,one is 12MHz ,the other is 50MHz ,when I transform a one bit signal from 12MHz to 50MHz ,the RTL viewer shows a very large delay between two registers that belong to 12MHz and 50MHz .Is there any settings in Quartus could reduce the delay?? thanks7 Replies
Altera_ForumThe delay is probably the transport delay from register to register. It shouldnt be a problem.
- Altera_Forum
What I am interested in is when I use the RTL viewer ,the registers using the same clock has no delay ,but when I use the different clocks there is a delay of 1.349ns ,and it is seen as a combinational logic (dict://key.0895dfe8db67f9409db285590d870edd/combinational%20logic) delay ,but it is just a wire .I don't know why .
thank you very much for your patience (dict://key.0895dfe8db67f9409db285590d870edd/patience) ! - Altera_Forum
I'm sorry, I don't understand what you are trying to achieve. There is always a delay between two registers. Why are you interested in the delay and what is the problem you are trying to solve?
- Altera_Forum
When I saw the delay between the two registers belonging to the 12M and 50M clocks,I don't know why there is a delay .If the registers using the same clock ,there if no delay which is saw by RTL vierer .
- Altera_Forum
This doesn't seem very long to me... especially since the proper clock domain crossing logic would add at least 2 cycles, which would be 40ns in the 12MHz -> 50MHz direction. What you you trying to do exactly?
- Altera_Forum
the delay is 1.349ns
- Altera_Forum
What do you mean by "very large delay"?
With the clock domain crossing logic that you need to place you'll have a few cycles of latency anyway.
