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Altera_Forum's avatar
Altera_Forum
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16 years ago

multiple clocks

Hi: I have two clocks in my design ,one is 12MHz ,the other is 50MHz ,when I transform a one bit signal from 12MHz to 50MHz ,the RTL viewer shows a very large delay between two registers that belo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

What I am interested in is when I use the RTL viewer ,the registers using the same clock has no delay ,but when I use the different clocks there is a delay of 1.349ns ,and it is seen as a combinational logic (dict://key.0895dfe8db67f9409db285590d870edd/combinational%20logic) delay ,but it is just a wire .I don't know why .

thank you very much for your patience (dict://key.0895dfe8db67f9409db285590d870edd/patience) !