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Altera_Forum's avatar
Altera_Forum
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16 years ago

multiple clocks

Hi: I have two clocks in my design ,one is 12MHz ,the other is 50MHz ,when I transform a one bit signal from 12MHz to 50MHz ,the RTL viewer shows a very large delay between two registers that belo...
Altera_Forum's avatar
Altera_Forum
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16 years ago

This doesn't seem very long to me... especially since the proper clock domain crossing logic would add at least 2 cycles, which would be 40ns in the 12MHz -> 50MHz direction. What you you trying to do exactly?