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Altera_Forum
Honored Contributor
Honored Contributormultiple clocks
Hi: I have two clocks in my design ,one is 12MHz ,the other is 50MHz ,when I transform a one bit signal from 12MHz to 50MHz ,the RTL viewer shows a very large delay between two registers that belo...
Altera_ForumHonored Contributor
Honored ContributorI'm sorry, I don't understand what you are trying to achieve. There is always a delay between two registers. Why are you interested in the delay and what is the problem you are trying to solve?
