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Honored Contributor
Honored Contributormultiple clocks
Hi: I have two clocks in my design ,one is 12MHz ,the other is 50MHz ,when I transform a one bit signal from 12MHz to 50MHz ,the RTL viewer shows a very large delay between two registers that belo...
Altera_ForumHonored Contributor
Honored ContributorWhen I saw the delay between the two registers belonging to the 12M and 50M clocks,I don't know why there is a delay .If the registers using the same clock ,there if no delay which is saw by RTL vierer .
