ModelSim does not show FIFO's signals

Hello horacioEsta,

>># ** Warning: (vsim-3473) Component instance "fifo1 : fifo512x32" is not bound.>>

This means that the FIFO instance from the Quartus library is not available for the simulation environment. Thats the reason why you see the signal are undefined. Please create a simulation library in Modelsim and copy the models from Quartus and the start the simulation. You will see the required signals at the output. To see how to make library please refer the Modelsim userguide, its pretty simple. All the best.

rsenthil78

Hello horacioEsta,

>># ** Warning: (vsim-3473) Component instance "fifo1 : fifo512x32" is not bound.>>

This means that the FIFO instance from the Quartus library is not available for the simulation environment. Thats the reason why you see the signal are undefined. Please create a simulation library in Modelsim and copy the models from Quartus and the start the simulation. You will see the required signals at the output. To see how to make library please refer the Modelsim userguide, its pretty simple. All the best.

rsenthil78

Yes that is right, I get the following message:

# ** Warning: (vsim-3473) Component instance "fifo1 : fifo512x32" is not bound.

What do I do about it?

Here is how I generate the reset for this core:

INT_RESET <= csi_reset or CONTROL_REG(31);

In the simulation, I can see the core getting reset when I write to the control register (bit 31).

On reset I see the simdata getting set to the right value.

Here is the FIFO:

--------------------------------------------------------------

COMPONENT FIFO512X32 IS

PORT

(

aclr : IN STD_LOGIC ;

clock : IN STD_LOGIC ;

data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

rdreq : IN STD_LOGIC ;

wrreq : IN STD_LOGIC ;

empty : OUT STD_LOGIC ;

full : OUT STD_LOGIC ;

q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

usedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)

);

END COMPONENT;

-------------------------------------------------------------

And here is how I got it connected:

-------------------------

FIFO1: FIFO512X32

PORT MAP(

aclr => INT_RESET,

clock => csi_clk,

data => SIM_DATA,

rdreq => FIFO_RD,

wrreq => FIFO_WE,

empty => STATUS_REG(9),

full => STATUS_REG(10),

q => FIFO_Q,

usedw => STATUS_REG( 8 DOWNTO 0)

);

-------------------------

I got some of the control lines going out to test points, just for monitor simulation purposes:

coe_tstpt(0) <= FIFO_WE;

coe_tstpt(1) <= FIFO_RD;

coe_tstpt(2) <= STATUS_REG(9);

coe_tstpt(3) <= STATUS_REG(10);

I can see that the STATUS bits 0 to 10 are undefined. Everything else is drive.

As I stated before, the FIFO model is not listed in the Testbench. This testbech was created by the SOPC Builder. Do I need to modify it to have the FIFO model in the testbench. How come ModelSim does not complain about it?

Thanks

--- Quote Start ---

The inputs are the control lines, rdreq, wrreq, and the data. These are all zero in the design. ModelSim shows that.

The FIFO is instanciated in the design. I don't see an entry in the testbech for the FIFO. I can't call myself a Modelsim expert.

--- Quote End ---

Hi,

that means the inputs of th Fifo are defined :confused:

Do the Fifo have a reset input ?

Kind regards

GPK

The inputs are the control lines, rdreq, wrreq, and the data. These are all zero in the design. ModelSim shows that.

The FIFO is instanciated in the design. I don't see an entry in the testbech for the FIFO. I can't call myself a Modelsim expert.

--- Quote Start ---

That is right, all input and output signals of this FIFO are undefined.

When I run the simulation, I only get "XXXXX", when I attempt to read the FIFO's status bits ( Empty flag, Full flag, wordsin).

Any ideas?

--- Quote End ---

Hi,

where is the instanciated ? In your design or in the testbench ?

Kind regards

GPK

Tipically the some/all of the output signals are only defined if all input signals are defined (!= X).

So please fix your testbench so that it provides valid inputs to the FIFO.

After that the outputs of the FIFO should be valid (!= X)

That is right, all input and output signals of this FIFO are undefined.

When I run the simulation, I only get "XXXXX", when I attempt to read the FIFO's status bits ( Empty flag, Full flag, wordsin).

Any ideas?