ModelSim does not show FIFO's signals

Here is how I generate the reset for this core:

INT_RESET <= csi_reset or CONTROL_REG(31);

In the simulation, I can see the core getting reset when I write to the control register (bit 31).

On reset I see the simdata getting set to the right value.

Here is the FIFO:

--------------------------------------------------------------

COMPONENT FIFO512X32 IS

PORT

(

aclr : IN STD_LOGIC ;

clock : IN STD_LOGIC ;

data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

rdreq : IN STD_LOGIC ;

wrreq : IN STD_LOGIC ;

empty : OUT STD_LOGIC ;

full : OUT STD_LOGIC ;

q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

usedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)

);

END COMPONENT;

-------------------------------------------------------------

And here is how I got it connected:

-------------------------

FIFO1: FIFO512X32

PORT MAP(

aclr => INT_RESET,

clock => csi_clk,

data => SIM_DATA,

rdreq => FIFO_RD,

wrreq => FIFO_WE,

empty => STATUS_REG(9),

full => STATUS_REG(10),

q => FIFO_Q,

usedw => STATUS_REG( 8 DOWNTO 0)

);

-------------------------

I got some of the control lines going out to test points, just for monitor simulation purposes:

coe_tstpt(0) <= FIFO_WE;

coe_tstpt(1) <= FIFO_RD;

coe_tstpt(2) <= STATUS_REG(9);

coe_tstpt(3) <= STATUS_REG(10);

I can see that the STATUS bits 0 to 10 are undefined. Everything else is drive.

As I stated before, the FIFO model is not listed in the Testbench. This testbech was created by the SOPC Builder. Do I need to modify it to have the FIFO model in the testbench. How come ModelSim does not complain about it?

Thanks