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Altera_Forum's avatar
Altera_Forum
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15 years ago

MAX7000 initialization problem

I am using Quartus II with a MAX7000s EPM7128. I am having a problem with an 8 bit latch not being initialized properly on power up of the CPLD. The latch outputs should be all zero after the cpld is powerd on, but instead it is loaded with random values.

The latch has a clear input which is fed by two signals through an OR gate. One signal is generated internally by other logic, the other signal comes in on the GCLRn pin of the CPLD and is fed by a power fail reset /power on reset circuit.

When the CPLD is powered on, the 8 bit latch has random bits set on the output. If I get rid of the OR gate and route only one of the signals (doesn't matter which one) to the latch clear pin (and ignore the other one) then the latch initializes to zero on power up. If I remove all connections to the clear pin on the latch it initializes correctly on power up.

The circuit works exactly as expected except for on power up. Any ideas?

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I'm not real familiar with the MAX devices. Do you have the "Power-up don't care" option set for the synthesis settings?

    Assignment->Settings->Analysis and Synthesis Settings->Power-up Don't Care (checkbox).

    You want to make sure that's cleared.

    You can also specify a power-up value for the latch either in the assignment editor or in the HDL code itself.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Well I did some more testing and it appears my celebration was premature. The latches now power up initialized to zero most of the time (probably 4 out of 5).

    I also set the power-up level in the assignment editor and it's not any better.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Are you sure there is not some event occurring that's causing values to be latched into the registers?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I am fairly certain that there is not any data that is being latched. The clock signals to the register are very specific. Also the registers will only get this random startup condition if the clear pin is connected to two signals through an OR gate. Also the OR gate to the clear pin works ok to reset the latches after everything has been powered up.

    So basically if I get rid of the power on reset and power fail reset everything works ok. Unfortunately these functions are a requirement.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It could be the external input is floating...touch it by hand and see...

    power-up state is a common problem if you depend on device's reset release after configuration. It is unreliable as vendors admit. To overcome that, I normally add my own powerup internal reset using say a counter that counts up from zero and stops at say 7 and for ever. This method needs a battle with optimisation and raises the question of how to get counter start at zero.

    Well, if you set powerup don't care to disabled you have high chance of success.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The external input is pulled to vcc with a 2k resistor.

    Is there anyway to implement an internal power up reset if there is no clock?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I thought we are talking about clked registers(though called latches). I understand you have clk and therefore you can run a counter at powerup reseting until count 6 and release reset at count 7.

    Without clk, I never tried that but I can imagine a non standard method of a signal followed by good delay then use logic for edge detection.

    After all, power up values are insignificant if you have your own external or internal reset.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    sorry, I used the term clock in a previous post to refer to the latch clock input, but actually it is not a clock but asynchronous logic. It is a completely asynchronous system.

    How can I add delay to a signal without a clock?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    try (and it is just a guess) several inverters to delay and invert a signal S to S_inverted.(you may need the keep attribute or get quartus to insert delay instead). Then detect edge transition:

    reset <= S and not S_inverted or not S and S_inverted;