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Altera_Forum
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15 years ago

MAX7000 initialization problem

I am using Quartus II with a MAX7000s EPM7128. I am having a problem with an 8 bit latch not being initialized properly on power up of the CPLD. The latch outputs should be all zero after the cpl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

sorry, I used the term clock in a previous post to refer to the latch clock input, but actually it is not a clock but asynchronous logic. It is a completely asynchronous system.

How can I add delay to a signal without a clock?