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Altera_Forum
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16 years ago

MAX7000 initialization problem

I am using Quartus II with a MAX7000s EPM7128. I am having a problem with an 8 bit latch not being initialized properly on power up of the CPLD. The latch outputs should be all zero after the cpl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I am fairly certain that there is not any data that is being latched. The clock signals to the register are very specific. Also the registers will only get this random startup condition if the clear pin is connected to two signals through an OR gate. Also the OR gate to the clear pin works ok to reset the latches after everything has been powered up.

So basically if I get rid of the power on reset and power fail reset everything works ok. Unfortunately these functions are a requirement.