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Altera_Forum
Honored Contributor
16 years agoMAX7000 initialization problem
I am using Quartus II with a MAX7000s EPM7128. I am having a problem with an 8 bit latch not being initialized properly on power up of the CPLD. The latch outputs should be all zero after the cpl...
Altera_Forum
Honored Contributor
16 years agoI thought we are talking about clked registers(though called latches). I understand you have clk and therefore you can run a counter at powerup reseting until count 6 and release reset at count 7.
Without clk, I never tried that but I can imagine a non standard method of a signal followed by good delay then use logic for edge detection. After all, power up values are insignificant if you have your own external or internal reset.