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Altera_Forum
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15 years ago

MAX7000 initialization problem

I am using Quartus II with a MAX7000s EPM7128. I am having a problem with an 8 bit latch not being initialized properly on power up of the CPLD. The latch outputs should be all zero after the cpl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm not real familiar with the MAX devices. Do you have the "Power-up don't care" option set for the synthesis settings?

Assignment->Settings->Analysis and Synthesis Settings->Power-up Don't Care (checkbox).

You want to make sure that's cleared.

You can also specify a power-up value for the latch either in the assignment editor or in the HDL code itself.

Jake