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Altera_Forum
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16 years ago

MAX7000 initialization problem

I am using Quartus II with a MAX7000s EPM7128. I am having a problem with an 8 bit latch not being initialized properly on power up of the CPLD. The latch outputs should be all zero after the cpl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

try (and it is just a guess) several inverters to delay and invert a signal S to S_inverted.(you may need the keep attribute or get quartus to insert delay instead). Then detect edge transition:

reset <= S and not S_inverted or not S and S_inverted;