MAX10 Single end I/O low/high speed bank frequency

In single-ended I/O use cases, the actual performance differences between low-speed and high-speed I/O pins are still unclear, particularly with respect to the maximum safe operating frequency. Are there any official documents or guidelines that describe this difference? In our case, the protocol is SPI with a required maximum operating frequency of 100 MHz. We would therefore like to ask: if the SPI signals are routed to low-speed I/O pins, what is the maximum frequency at which stable operation can realistically be achieved? Are there any recommended limits, characterization data, or application notes that address this scenario?