Forum Discussion
New ContributorMAX10 Single end I/O low/high speed bank frequency
In single-ended I/O use cases, the actual performance differences between low-speed and high-speed I/O pins are still unclear, particularly with respect to the maximum safe operating frequency. Are there any official documents or guidelines that describe this difference? In our case, the protocol is SPI with a required maximum operating frequency of 100 MHz. We would therefore like to ask: if the SPI signals are routed to low-speed I/O pins, what is the maximum frequency at which stable operation can realistically be achieved? Are there any recommended limits, characterization data, or application notes that address this scenario?
6 Replies
FvMSuper Contributor
Hi,
differences between low- and high-speed IO banks only apply to LVDS and DDR IO standards. 100 MHz SPI will presumedly use single-ended IO and isn't restricted to specific banks.
Regards
Frank
AaronHi Farabi,
But in pin out file, the pins are still divided into low-speed and high-speed categories.
So have any MAX10 single end signals frequency limit or performance data?
Thanks.
Best Regards,
Aaron Hsu
Farabi_AlteraRegular Contributor
Hello,
MAX10 does not have transceiver block(HSIO), like other FPGA variance - Cyclone 10, Stratix 10, Agilex series etc. So, MAX10 is consider low speed device.
regards,
Farabi
- FvM
The terms low- and high-speed IO are nevertheless used in datasheet, e.g. for banks with different LVDS features.
- Farabi_Altera
Hello Aaron,
SPI will use single-ended IO which can be used in any banks. Please refer to datasheet for speed.
regards,
Farabi
