Forum Discussion
Aaron
New Contributor
New ContributorMAX10 Single end I/O low/high speed bank frequency
In single-ended I/O use cases, the actual performance differences between low-speed and high-speed I/O pins are still unclear, particularly with respect to the maximum safe operating frequency. Are t...
Farabi_Altera
Regular Contributor
Regular ContributorHello,
MAX10 does not have transceiver block(HSIO), like other FPGA variance - Cyclone 10, Stratix 10, Agilex series etc. So, MAX10 is consider low speed device.
regards,
Farabi
FvM
Super Contributor
Super ContributorThe terms low- and high-speed IO are nevertheless used in datasheet, e.g. for banks with different LVDS features.
- Farabi_Altera
Hello Aaron,
SPI will use single-ended IO which can be used in any banks. Please refer to datasheet for speed.
regards,
Farabi
- Farabi_Altera
Hi Aaron,
Can refer here: https://docs.altera.com/r/docs/683751/24.1/max-10-general-purpose-i/o-user-guide/max-10-i/o-elements
regards,
Farabi
