Forum Discussion
Honored ContributorMAX10 ADC doesn't start during power on
I'm using MAX10 ADC to measure on board voltages. The ADC IP operates normally when the design was programmed using JTAG USB Byte Blaster with SOF file. When same design is programmed using POF file, only ADC IP doesn't run while other logic operates normally. I generated ADC IP as "ADC Control Core Only". Anyone ran into this issue?
Thanks,15 Replies
Altera_ForumAre you convinced you're using the right .sof to generate your .pof programming file? If you have part of your design behaving as expected might you have incorrectly used a previous, older .sof file?
I've never experienced a .sof / .pof discrepancy as you describe. Cheers, Alex- Altera_Forum
then restart again and again
- Altera_Forum
Thanks for the reply Alex.
The POF is generated from SOF. This was my time running into this issue. I actually debugged Altera's IP until I got down to ADC hard IP, and this indicated that ADC hard IP was not generated correct clocks. So, I started to check the schematic, and I found the issue. The board designer connected VCCIO1A and VCCIO1B to wrong rail. I'm not sure how this rail pins are used for ADC, but it's related. When I tried my design on DECA development board, the POF file does work. This concludes this bug. I hope this thread can be useful for other engineers. Regards, - Altera_Forum
I have the same issue, with a 10m50 MAX 10 adc. The .sof works fine but the .pofadc does not! YES I am using the correct files. I connected VCCIO1A and B to the same rail, but no success. I have noticed that the 'power down' flag is set, what is that? I found this in the Verilog files for the adc.
I have tried a DECA board and it works fine, I have also tried a BeMicro board and it works fine in both .sof and .pof modes. NOTE: the power rails for the DECA and BEMicro are different, I tried both on my board with no luck... YUCK.... - Altera_Forum
Do the power supplies you are using for the device meet the requirements for MAX 10? Refer to the "max 10 power management user guide (https://www.altera.com/literature/hb/max-10/ug_m10_pwr.pdf)".
--- Quote Start --- If the ramp time, tRAMP, is not met, the MAX 10 device I/O pins and programming registers remain tristated, during which device configuration could fail. --- Quote End --- It does not state exactly how this "could" fail. However, it may well be possible that partial configuration - of the logic - might occur and the ADC suffers. Subsequently programming it with a .sof, once the rails are all up and steady, could rectify this. So, refer to figure 2-3 on page 2-6 and confirm your device rails comply. Cheers, Alex - Altera_Forum
Hi Alex,
Here is interesting part of this problem. When you program the part using POF, the part restarts itself using the POF file. Based on the other development boards, the part does restart after the POF configuration. This behavior excludes the possibility of power up sequence issue. This remains whether there is enough current for transient during the configuration from POF. From the power management user guide, it states that 680mA is maximum power transient current. Can transient current can cause ADC IP configuration to fail? Thanks, K - Altera_Forum--- Quote Start --- interesting part of this problem. When you program the part using POF, the part restarts itself using the POF file --- Quote End --- Indeed. Interesting. I've just confirmed this for myself as well. So, as you say, no power up issue appears to be relevant. How are you instantiating and connecting up your ADC module? Specifically, how are you controlling the 'reset' and the 'pll locked' signals? Could it be that, for your chosen part, not controlling these correctly could cause the issue? I've tried modifying how both these are controlled but can't reproduce the ADC lockup on the only MAX 10 board I have - a max 10 fpga evaluation kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-max-10-evaluation.html). The ADC always works, regardless of both what I do with these signals and how the FPGA is configured. However, could there be a problem in certain devices regarding the reset and/or locked signals to the ADC block? Cheers, Alex
- Altera_Forum
I probed around and found that a PWRDOWN signal in a FSM was always hi, thus keeping the ADC off when .pof is used, but ok when .sof. What is happening??? Is this an Altera problem??
- Altera_Forum
Here is the line in the verilog FSM for the ADC module only:
night_adc:u0|night_adc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|ctrl_state.PWRDWN_DONE This is hi when the .pof is programmed in the MAX10. - Altera_Forum
Hi Kattice,
I saw that you have used the ADC control Core only as the core variant. I'm using the same core variant but I'm not able to get my ADC working properly. I've enabled the channel CH 0 of ADC1 and have connected the parameters as required but when I'm giving a signal from a signal generator response_data port is showing nothing. Could you please help me with this issue ? Is there any other configuration that needs to be done while using the ADC control core ? Thanks,
