sean793
New Contributor
New ContributorMAX10 1.8V LVDS Output before, during, after configuration driving LVDS 1.5V VCCIO Inputs
As a follow up to this post
which covers the behavior of the MAX10's 1.8VLVDS input, I would like to know if the 1.8V LVDS outputs also have similar behavior to the inputs before, during and after configuration. That is, does the output have a weak pull-up to 1.8V and is there any danger in driving an FPGA device that has an LVDS input that operates from 1.5V VCCIO.
-Sean
Hi Sean,
Refer to the link below on the MAX10 I/O pin behaviour throughout the configuration sequence:
This should apply to both the input and output pins.
Regards,
Aqid
