Honored ContributorHello!
What Max speed of capture of analog data we can achieve using Altera FPGA devices? Digitized data will be stored in memory and then to be transferred through PCI-E. What max bandwidth of DDR-II and PCI-E core? Whether there are reference designs? Thanks!
Honored ContributorHi,
for your first question, it depends on the ADC that you choose. The FPGA doesn't have a built in ADC. (although there are some ideas regarding using the SSTL-type input with a VREF to act as a comparator, and then vary the VREF to find the signal level.) The FPGA's inputs can handle any ADC that I know of. Some newer ADCs (like from Analog Devices) use LVDS outputs, and Altera FPGAs can take up to 1000 mbps on the LVDS inputs. So that won't be your limiting factor. Altera has a reference design showing the use of PCIe and DDR2 memory on the Altera PCIe dev kit board. Check it out here: http://www.altera.com/end-markets/refdesigns/sys-sol/indust_mil/ref-pciexpress-ddr2-sdram.html have fun! GregorHonored ContributorHello Gregor! I'm going to use Atmel ADCs. What do you think about realizing multiplexor in FPGA to switch between ADCs(and increase sampling so). Will be it work precisely?
"(although there are some ideas regarding using the SSTL-type input with a VREF to act as a comparator, and then vary the VREF to find the signal level.)" It's something new for me. Where I can find information about it? Thanks!Honored ContributorYou need to use an ADC external. The sky is the limit on how much data you can capture and is only limited by your ability to process or transfer that data.
Can you give a little more detail about the analog signal you are trying to capture?Honored ContributorHere's a system that samples at 1GHz:
http://www.ovro.caltech.edu/~dwh/correlator/index.html I was at the Embedded Systems Conference class given by the designer (David Hawkins) and the system in the above link is being replaced by a Stratix II based system that will do 983 TMAC/s. As far as the maximum bandwidth of the DDR-II and PCI-e, you can determine these pretty quickly through their respective data sheets. Although, maximum bandwidth, and real-world data throughput are two different things.Honored ContributorI agree that you can calculate the PCIe and DDR II bandwidth easily. Based on the following comment.
"The COBRA Digitizer boards digitize the downconverter output (500MHz to 1GHz) at a 1GHz clock frequency to 2-bits of resolution. The digitizer ICs internally demultiplex this data by two producing 4-bits at 500MHz. ECL logic on the digitizer module then demultiplex this further to 32-bits at 62.5MHz, and then convert the data the CMOS/TTL logic levels. The CMOS/TTL data is then received by the digitizer board FPGAs (field programmable gate arrays)." It seems like the ADC used presents the data to the FPGA at a rate of 62.5MHz at CMOS/TTL levels. The Altera devices can handle data rates much faster than that. Depending on the IO standard used you can expect the FPGA to receive data at rates up to 1 Gbps per single IO. It all depends on the IO standard of the ADC. I am not familiar with the ADCs used in this sort of application. But, the "digitizer" manufacturers generally design their high-end ADCs to hook up to FPGAs. Hope this helps.Honored Contributor
